Multi-chip (or multi-die) memory packages contain a number of individual memory devices, e.g., that may be stacked one above another. Each memory device may be a NAND or a NOR flash memory device, dynamic random access memory (DRAM) device, static random access memory (SRAM) device, or the like. A multi-chip memory package typically includes a memory controller for accessing and controlling each memory device. The memory controller usually includes external inputs and outputs for coupling to a host device, such as a processor, a memory controller in a personal computer, a processor of tester hardware, etc. Problems arise during testing after the multi-chip memory package is assembled, such as during back-end testing as part of the manufacturing process or during testing of a defective multi-chip memory package, e.g., returned by a user. Such problems occur because internal functioning of the memory devices cannot be accessed directly through the external inputs and outputs of the multi-chip memory package.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative test methods for multi-chip memory packages.